What is mean of fast/slow 0C/85C model?

The actual timing characteristics of the chips are subject to PVT (process, voltage, temperature) variations.

Process: no two chips are equal. For a given FPGA speedgrade, some chips will be faster, some slower.

Voltage: higher Vcc makes the chip faster, lower Vcc makes the chips slower.

Temperature: lower T makes the chips faster, higher T makes the chip slower (0C is 0ºC, 85C is 85 ºC).

To ensure that the design will actually work in the real world, with different chips, subject variations in Vdd and different temperatures, STA tools usually run the analysis for 3 cases, known as corners: an extreme fast case, an extreme slow case and a typical case.

Not quite.

For a given process corner (ie, holding the process factor constant) and fixed voltage the FPGA will run faster at 0'C than it does at 85'C. This is a characteristic of the CMOS process.

Again holding the process constant and at a constant die temperature, the FPGA will run faster at a higher voltage than at a lower voltage (within the operating voltage limits of the design).

And lastly, for any fixed temperature and fixed voltage, there will be some FPGA die that run faster and some slower. This is process variability.

So to robustly test a design over all operating parameters, one might use a fast process part running at low temperature and maximum voltage. And then use a slow process part running at high temperature and minimum operating voltage.

Unless you are a high volume corporate customer of Altera's you won't ever be able to get 'fast' and 'slow' process corner parts (other than selecting -6 or -8 speed grades yourself). But you can test at high and low temp, and at high and low operating voltage.

Commercial product developers (of which I was one) routinely do this multiple corner testing as part of the DVT (design validation test) process prior to volume manufacturing.

Hi,

doing a quick lookup at ALTERA themselves...

As you already figured out, the timing analysis is performed to check for violation with the fastest speedgrade "type" of FPGA defined in the project and with the slowest for the upper and lower temperature limit (0C and 85C indicate a commercial grade device...)

As signals are running around the chip "through" combinatorical and registered logic, there may be violations with the slowest as well as the fastest speedgrade....

Or as written in Quartus II v12 Handbook, chapter 6:

"Multicorner Analysis:

The TimeQuest analyzer performs multicorner timing analysis to verify your design

under a variety of operating conditions—such as voltage, process, and temperature—

while performing static timing analysis.."

You have already been answered but I can visualise the timing space as a triangle with 3 corners, top corner being best for timing:

corner 1 is the 0C fast model. Best for timing

corner 2 is 0c slow model

corner 3 is 85C slow model

All cases fall on the triangle space.

Definitions are given by altera as follows:

0C fast: fastest silicon + highest voltage + 0C

0C slow: slowest silicon + lowest voltage + 0C

85C slow: slowest silicon + lowest voltage + 85C

Note: voltage within allowable range, silicon within chosen speed grade

since corner 1 is best, I note that timequest gives fmax for corner 2 & 3 but not corner 1

To be more accurate, it is not a single triangle but imagine three axes say x,y,z where x is for temperature, y for voltage, z for silicon. at every case you can choose 3 points, one on each axis and draw a triangle. The centre of a given triangle becomes the timing space of your case. The whole set of triangles is the full timing space.

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corner 1 is the 0C fast model. Best for timing

corner 2 is 0c slow model

corner 3 is 85C slow model

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"Best" is in the eye of the beholder. It is more correctly the "Fast" model, i.e., the time delays are shortest.

If you take a look at the timequest.pdf document I posted to this thread,

http://www.alteraforum.com/forum/showthread.php?t=31457

and keep flipping between pages 38 and 39, you'll get a visualization of the difference between slow and fast timing models at the I/Os of an FPGA.

The signals from the fast model leave sooner than the slow model. This means that an external register capturing data from the fast model would have more setup time, and less hold time than the slow model. Depending on your application, that might be a bad or good thing, hence "best" is subjective.

A "complete" timing analysis involves taking the worst-case timing parameters from all corner cases, and making sure your design meets timing for them all.

Cheers,

Dave

Thanks Dave. I actually quoted from an Altera document the word "best". Here is the quote:

[Opposite to the Slow 85°C and 0°C operating conditions, the Fast 0°C provides bestcase operating conditions for the device and results in overall shorter delays in the device. This condition is ideal for performing a hold and removing checks in static timing analysis].

I will try to digest your further notes.

Kaz

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"Best" is in the eye of the beholder. It is more correctly the "Fast" model, i.e., the time delays are shortest.

If you take a look at the timequest.pdf document I posted to this thread,

http://www.alteraforum.com/forum/showthread.php?t=31457

and keep flipping between pages 38 and 39, you'll get a visualization of the difference between slow and fast timing models at the I/Os of an FPGA.

The signals from the fast model leave sooner than the fast model. This means that an external register capturing data from the fast model would have more setup time, and less hold time than the slow model. Depending on your application, that might be a bad or good thing, hence "best" is subjective.

A "complete" timing analysis involves taking the worst-case timing parameters from all corner cases, and making sure your design meets timing for them all.

Cheers,

Dave

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OK seems I can digest these io notes. True but you actually mean a fast io register is more likely to support an external device setup requirement than meets its hold requirement. Certainly true but depends heavily on device requirement relative to clock edge (if setup/hold are viewed from pin perspective)

Hi Kaz,

The main point I was trying to point out to the original poster was that all of the timing models need to be used.

Register-to-register paths within the FPGA will undergo similar changes in timing as shown in the figures in the document I referred to. Personally I find a timing diagram easier to interpret, so I figured I'd post a link to that doc.

Cheers,

Dave

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I have vague idea that cooling below 0C may start to reverse speed improvement effect.

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I have a hard enough time keeping the die temperature below the maximum temperature, so I won't have to worry about that effect :)