What is mean of fast/slow 0C/85C model?

Hi,

doing a quick lookup at ALTERA themselves...

As you already figured out, the timing analysis is performed to check for violation with the fastest speedgrade "type" of FPGA defined in the project and with the slowest for the upper and lower temperature limit (0C and 85C indicate a commercial grade device...)

As signals are running around the chip "through" combinatorical and registered logic, there may be violations with the slowest as well as the fastest speedgrade....

Or as written in Quartus II v12 Handbook, chapter 6:

"Multicorner Analysis:

The TimeQuest analyzer performs multicorner timing analysis to verify your design

under a variety of operating conditions—such as voltage, process, and temperature—

while performing static timing analysis.."