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"Best" is in the eye of the beholder. It is more correctly the "Fast" model, i.e., the time delays are shortest.
If you take a look at the timequest.pdf document I posted to this thread,
http://www.alteraforum.com/forum/showthread.php?t=31457 and keep flipping between pages 38 and 39, you'll get a visualization of the difference between slow and fast timing models at the I/Os of an FPGA.
The signals from the fast model leave sooner than the fast model. This means that an external register capturing data from the fast model would have more setup time, and less hold time than the slow model. Depending on your application, that might be a bad or good thing, hence "best" is subjective.
A "complete" timing analysis involves taking the worst-case timing parameters from all corner cases, and making sure your design meets timing for them all.
Cheers,
Dave
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OK seems I can digest these io notes. True but you actually mean a fast io register is more likely to support an external device setup requirement than meets its hold requirement. Certainly true but depends heavily on device requirement relative to clock edge (if setup/hold are viewed from pin perspective)
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