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Altera_Forum
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13 years ago

What is mean of fast/slow 0C/85C model?

There are three models in STA, it seems there is little reference from Altera to explain what is the mean of these and which is most important (I guess this depends on where the FPGA chip is used). S...
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Altera_Forum
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13 years ago

Hi Kaz,

The main point I was trying to point out to the original poster was that all of the timing models need to be used.

Register-to-register paths within the FPGA will undergo similar changes in timing as shown in the figures in the document I referred to. Personally I find a timing diagram easier to interpret, so I figured I'd post a link to that doc.

Cheers,

Dave