virtual pins

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hi all I am a newbee in designing with FPGA.

In our company we are redesignig a multiplexer. Stating on a old projects Quartus II gives several timing warnings.

Why if I place a pin in a low level bdf file, and outside the block it is not connected this can change the sinthesis and fitting process. I suppose there is a change in sinthesis and fitting because it happend that simulation result changes simply adding a pin buried in the hierarchy and not connected. This is completely illogical for me.

Please help me

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Hi,

is it an input or output pin ? I would assume that Quartus detects a change in your design and starts a complete new run. That means elaboration, synthesis and P&R. Quartus did not go through all the design files and look what changed. Every change in a low level file could have a impact to higher level files. The simplest way for Quartus to handle this is to run a new synthesis. As long as the runtime of the tool or timing closure is not an issue it should be not a problem. Otherwise you should look to design partitions, but that's a more complex flow and not recommanded when you are starting with Qurtus.

Kind regards

GPK

No the pins are placed only to have some "test point" during a timing simulation. If I compile the lower level bdf of my project I can place this pins as "virtual pins2 and i have no change in simulation result on other pins with or without them. rising the level in the hierarchy this pina are obviously not assigned as virtual pin but it the simulation results change with those pins or without those pins. I really don't understand. For your information the project was developed on max plus II and early version of quartus on a APEX device and they did have any kind of problems.

Tx am in trouble with this.

Regards

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No the pins are placed only to have some "test point" during a timing simulation. If I compile the lower level bdf of my project I can place this pins as "virtual pins2 and i have no change in simulation result on other pins with or without them. rising the level in the hierarchy this pina are obviously not assigned as virtual pin but it the simulation results change with those pins or without those pins. I really don't understand. For your information the project was developed on max plus II and early version of quartus on a APEX device and they did have any kind of problems.

Tx am in trouble with this.

Regards

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Hi Stefano,

are the test points connected to registers or logic ? When you integrate your lower level bdf in the toplevel design did you assign the test points again as virtual pins ?

Kind regards

GPK

Hi Plets,

yes on the higher hierarchy I place the those test pins as virtual pins. During the complitation I see the message that some virtual pins are removed because they are buried in the hierarchy, but on the test pins on the top level the assigment is no removed. THe strange thing is a change in the simulation results on the other output or driving logic pins. In this situation it impossible to debug a circuit...

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Hi Plets,

yes on the higher hierarchy I place the those test pins as virtual pins. During the complitation I see the message that some virtual pins are removed because they are buried in the hierarchy, but on the test pins on the top level the assigment is no removed. THe strange thing is a change in the simulation results on the other output or driving logic pins. In this situation it impossible to debug a circuit...

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Hi Stefano,

ok, we are talking about gatelevel simulation ?

Kind regards

GPK

I'm not clear, what you're complaining about. Introducing hardware debug features, either by SignalTap II, SignalProbe or user defined debug pins always changes the place & route of a design and timing as well. Applying partition lock to an entity including the debug connections would be the only way to freeze the (partition internal) routing.

Your original post has been about timing conflicts. Why not trying to fix these conflicts? Timing violations mean, that the design is working at the speed margins. Introducing one pipeline level at the most critical place usually relaxes it sufficiently. It may be of course also a case of not well considered timing constraints (e.g. you omitted possible multi-cycle assignments).

Hi all,here more information.

My design includes the following main blocks and the device is a EP2C15

1)16x2Mbit multiplexer

2)16X2mbit demultiplexer

3)I2S to 2Mbit Coder

4)2 2Mbit ro I2S decoder

all block come from old projects

If i compile the whlo project i have a bunch on hold violations. and it does not work.

I am trying to identify the problem due to the not timing closure but also with woking with few buried block internally at the multiplexer where the hold violation is higher (about 14 ns) if with some virtual pins used ad Test point in the simulation (gate level timing) I see some changes in the results with or without those debug pins and the debug is impossible.

I hope the situation is more clear now.

Regards.