virtual pins

Hi all,here more information.

My design includes the following main blocks and the device is a EP2C15

1)16x2Mbit multiplexer

2)16X2mbit demultiplexer

3)I2S to 2Mbit Coder

4)2 2Mbit ro I2S decoder

all block come from old projects

If i compile the whlo project i have a bunch on hold violations. and it does not work.

I am trying to identify the problem due to the not timing closure but also with woking with few buried block internally at the multiplexer where the hold violation is higher (about 14 ns) if with some virtual pins used ad Test point in the simulation (gate level timing) I see some changes in the results with or without those debug pins and the debug is impossible.

I hope the situation is more clear now.

Regards.