virtual pins

I'm not clear, what you're complaining about. Introducing hardware debug features, either by SignalTap II, SignalProbe or user defined debug pins always changes the place & route of a design and timing as well. Applying partition lock to an entity including the debug connections would be the only way to freeze the (partition internal) routing.

Your original post has been about timing conflicts. Why not trying to fix these conflicts? Timing violations mean, that the design is working at the speed margins. Introducing one pipeline level at the most critical place usually relaxes it sufficiently. It may be of course also a case of not well considered timing constraints (e.g. you omitted possible multi-cycle assignments).