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Altera_Forum
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16 years ago

virtual pins

hi all I am a newbee in designing with FPGA. In our company we are redesignig a multiplexer. Stating on a old projects Quartus II gives several timing warnings. Why if I place a pin in a low le...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Hi Plets,

yes on the higher hierarchy I place the those test pins as virtual pins. During the complitation I see the message that some virtual pins are removed because they are buried in the hierarchy, but on the test pins on the top level the assigment is no removed. THe strange thing is a change in the simulation results on the other output or driving logic pins. In this situation it impossible to debug a circuit...

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Hi Stefano,

ok, we are talking about gatelevel simulation ?

Kind regards

GPK