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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL variable indexed array improperly munched

Quartus synth not recognizing variable indexed arry, i.e.

TYPE dly2 IS ARRAY (0 to 6) OF SIGNED(17 downto 0);

SIGNAL intline: dly2;

SIGNAL int_time: std_logic_vector(2 downto 0);

dlyout <= intline(to_integer(unsigned(int_time)));

intline gets totally munched because the synthesis tool does not see that any of the intline registers are connected to outputs. This is an error.

Precision synthesis does this correctly, as did Leonardo and even Galileo - ancient Exemplar tools.

Anyone else bump into this?

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    no, but why is int_time a std_logic_vector and not an integer?

    and are you using numeric_std or std_logic_arith librarby?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi.

    Int_time is a std_logic because it comes from another block of registers that are defined that way. I've tried assigning the to_integer(unsigned(int_time)) to an integer (index) and then using dly(index) - same thing

    I'm using numeric_std library.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You should post a minimal complete example code, that allows to reproduce the problem. I'm using a lot of similar constructs and they are generally understood by Quartus as expected. There may be a problem caused by the 0 TO 6 range, you can try if the result changes when you restrict the assignment to valid codings of int_time.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    One test case issue is that if I just build the module with the construct it doesn't get munched because the inputs are directly connected to pins.

    --- Quote End ---

    Registering the signals should be sufficient to overcome this problem.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    That was my thought, too, and what I did intially, but Quartus tracked it back thru the intervening regs to the pins. Pretty smart.

    Thanks,
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You can double register the data to avoid usage of output and input registers inside the entity.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Okay - I'll remember next time, but the shift definitely disconnected from inputs, also, and exposed the variable indexed array problem.