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Altera_Forum
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15 years ago

VHDL variable indexed array improperly munched

Quartus synth not recognizing variable indexed arry, i.e. TYPE dly2 IS ARRAY (0 to 6) OF SIGNED(17 downto 0); SIGNAL intline: dly2; SIGNAL int_time: std_logic_vector(2 do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi.

Int_time is a std_logic because it comes from another block of registers that are defined that way. I've tried assigning the to_integer(unsigned(int_time)) to an integer (index) and then using dly(index) - same thing

I'm using numeric_std library.

Thanks