Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL variable indexed array improperly munched

Quartus synth not recognizing variable indexed arry, i.e. TYPE dly2 IS ARRAY (0 to 6) OF SIGNED(17 downto 0); SIGNAL intline: dly2; SIGNAL int_time: std_logic_vector(2 do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

One test case issue is that if I just build the module with the construct it doesn't get munched because the inputs are directly connected to pins.

--- Quote End ---

Registering the signals should be sufficient to overcome this problem.