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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL variable indexed array improperly munched

Quartus synth not recognizing variable indexed arry, i.e. TYPE dly2 IS ARRAY (0 to 6) OF SIGNED(17 downto 0); SIGNAL intline: dly2; SIGNAL int_time: std_logic_vector(2 do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

That was my thought, too, and what I did intially, but Quartus tracked it back thru the intervening regs to the pins. Pretty smart.

Thanks,