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Altera_Forum
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15 years ago

VHDL variable indexed array improperly munched

Quartus synth not recognizing variable indexed arry, i.e. TYPE dly2 IS ARRAY (0 to 6) OF SIGNED(17 downto 0); SIGNAL intline: dly2; SIGNAL int_time: std_logic_vector(2 do...
Altera_Forum's avatar
Altera_Forum
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15 years ago

You should post a minimal complete example code, that allows to reproduce the problem. I'm using a lot of similar constructs and they are generally understood by Quartus as expected. There may be a problem caused by the 0 TO 6 range, you can try if the result changes when you restrict the assignment to valid codings of int_time.