VHDL sensitivity list - synthesis

Question

Hello,

Is it fairly confirmed that Quartus ignores the sensitivity list of a process for synthesis, like many other tools?

Sources online and in books are ambiguous on this subject, but it appears that tools usually just check the sensitivity list for missing signals and issue warnings, but otherwise the sensitivity list affects synthesis in no way.

VHDL 2008 even introduced the all keyword inside sensitivity lists to "brush away" this issue altogether, it seems.

Thanks in advance

altera_forum · Answer

Quartus ignores sensitivity lists for synthesis. The logic produced is defined by the code signals used within the process.

From memory I cannot remember whether Quartus even produces a warning.

Modelsim on the other hand does make use of sensitivity lists so missing signals in the list can produce different behaviour between simulation and synthesis.

altera_forum · Answer

Sensitivity lists are there purely for simulation - they let the simulator know when a process needs to be executed. This saves alot of processor time because it doesnt need to re-evaluate every process whenever a signal changs.

Synthesis however, just creates logic from the code you have written following template guidelines, so sensitivity is ignored completely. Quartus WILL give a warning when a sensitity is incomplete. the code describes actualy hardware, so if you write something like this:

process(a)

begin

b <= c;

end process;

in VHDL this actually means b is only updated when a changes, but that isnt really possible in hardware.

altera_forum · Answer

Yes, for the same reason, having an incomplete sensitivity list might cause behavior to differ from what you see in simulation. Because of this, it is always a good idea to specify a properly defined sensitivity list. A combinational logic process should be made sensitive to  every signal you have on the right side of an assignment inside the process. By making this change, you will avoid simulation-synthesis mismatches.

altera_forum · Answer

Also it's a big assumption that all synthesis tools will always ignore the sensitivity list. Some may ignore it; some may instantiate a latch.

altera_forum · Answer

Can you give an example, where you either experienced or suspect different behaviour of synthesized code depending on sensitivity lists?

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VHDL sensitivity list - synthesis

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