Altera_ForumHonored Contributor17 years agoVHDL sensitivity list - synthesis Hello, Is it fairly confirmed that Quartus ignores the sensitivity list of a process for synthesis, like many other tools? Sources online and in books are ambiguous on this subject, but i...Show More
Altera_ForumHonored Contributor11 years agoHi batfink, I always thought so, but can you provide a counter-example? Thanks,
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: