VHDL sensitivity list - synthesis

Sensitivity lists are there purely for simulation - they let the simulator know when a process needs to be executed. This saves alot of processor time because it doesnt need to re-evaluate every process whenever a signal changs.

Synthesis however, just creates logic from the code you have written following template guidelines, so sensitivity is ignored completely. Quartus WILL give a warning when a sensitity is incomplete. the code describes actualy hardware, so if you write something like this:

process(a)

begin

b <= c;

end process;

in VHDL this actually means b is only updated when a changes, but that isnt really possible in hardware.