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Altera_Forum
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17 years ago

VHDL sensitivity list - synthesis

Hello, Is it fairly confirmed that Quartus ignores the sensitivity list of a process for synthesis, like many other tools? Sources online and in books are ambiguous on this subject, but i...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Yes, for the same reason, having an incomplete sensitivity list might cause behavior to differ from what you see in simulation. Because of this, it is always a good idea to specify a properly defined sensitivity list. A combinational logic process should be made sensitive to every signal you have on the right side of an assignment inside the process. By making this change, you will avoid simulation-synthesis mismatches.