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Altera_Forum
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13 years ago

VHDL getting Array elements with std_logic_vector

Hello,

I'm having some trouble synthesizing my code, I'm running out of logic cells on my DE2 Altera board.

I want to use the values from 4 std_logic_vectors(7 downto 0) to retrieve the elements of an array, CollisionReg which consists of 119 std_logic_vectors(159 downto 0). I'm doing this by converting the std_logic_vectors to integer using to_integer( unsigned( some std_logic_vector ). If I remove the integer conversions, I can compile fine. I've also tried storing the conversion into some integer variable of a fixed range 0 to 160, but it doesn't help. Is there a reason why integer conversion is taking so many logic cells? Is there a better way for me to do this?

My code creates a matrix equal to the screen resolution and detects if a coordinate on the screen has been travelled before. Any help would be appreciated, thanks!

entity CoordinateMatrix is
port(
        XHead: in std_logic_vector(7 downto 0);
        YHead: in std_logic_vector(7 downto 0);
        XTail: in std_logic_vector(7 downto 0);
        YTail: in std_logic_vector(7 downto 0);
        LoadCM: in std_logic;
        initCM: in std_logic;
        CLK: in std_logic;
        didCollide: out std_logic);
end;
architecture behavioural of CoordinateMatrix is
    type CMArray is array(119 downto 0) of std_logic_vector(159 downto 0);
    signal CollisionReg: CMArray;
    
begin
collisionMatrix: process(CLK) 
begin
    if(rising_edge(clk)) then
        if(LoadCM = '1') then
            if(initCM = '1') then        
                -------********* PROBLEM HERE
                didCollide <= CollisionReg(to_integer( unsigned( XHead)))(to_integer( unsigned( YHead))); --return old value    
                CollisionReg(to_integer( unsigned( XHead)))(to_integer( unsigned( YHead))) <= '1'; --update to already been here
                CollisionReg(to_integer( unsigned( XTail)))(to_integer( unsigned( YTail))) <= '0'; --remove last pixel of snake
                --------------------------------
            else
                for i in 119 downto 0 loop
                    for y in 159 downto 0 loop
                        if(i = 0 OR i = 119 OR y = 0 or y = 159) then --border always occupied
                            CollisionReg(i)(y) <= '1';
                        else
                            CollisionReg(i)(y) <= '0';
                        end if;
                    end loop;
                end loop;    
                
            end if;
        end if;
    end if;
end process;

20 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Thank you for the prompt respond. Can you please help as to what and where I should be looking for this infomation in the specs?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    The specs for your project are your own. As you get more experienced, it gets easier to understand how different elements work and how many resources they will use.

  • Altera_Forum's avatar
    Altera_Forum
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    You'll find the logic element, RAM and DSP count in the overview tables at the begin of each FPGA device handbook.

  • Altera_Forum's avatar
    Altera_Forum
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    FVM and Tricky

    Thank you for responding.

    I am currently using a Cyclone II EP2C70 device. The Handbook indicates that there are 68416 LE's.

    So based on the above discussion of 160 X 120 8 bit registers would require 160*120*8 = 153600 LE's. But since device has only 68416 LE's this is practically impossible.

    Am I correct.

    My understanding is that each LE has 1 bit flip flop (1 programmable register)

    Appreciate your feedback
  • Altera_Forum's avatar
    Altera_Forum
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    yes, that would be a problem. But why do you need registers. Could you use a RAM instead?

  • Altera_Forum's avatar
    Altera_Forum
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    Tricky,

    Currently I am using the on chip RAM for other purpose. But ultimately I do intend to go to off chip RAM. I am still learning of accessing and managing off board RAM.

    Thank you for your help
  • Altera_Forum's avatar
    Altera_Forum
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    Are you using all of them? Your "registers" would only use 40 of the M4ks available.

    What are you storing here? basically, you're not going to be able to store it in registers. And if you cant store it in M4K blocks, then your only choice is the external ram.
  • Altera_Forum's avatar
    Altera_Forum
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    Tricky,

    Currently I have part of an image stored in M4K ram that I read and process. I understand this not a good design. I do intend to ultimately store the data on external RAM. I was hoping to read the complete image into a array and process the image. As I learn more about the characteristics of the FPGA I am better understanding my limitations.

    Can you please elaborate on the follow statement "your "registers" would only use 40 of the m4ks available"

    Thank you for the feedback.
  • Altera_Forum's avatar
    Altera_Forum
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    Yes I could, but currently I have the M4K filled by a 1000 x 16 x (8bit) data array.Knowing what I know I intend to complete the work that I have done, then work on learning more about external memory processing. This way I can store multiple images and then process them efficiently.