Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

VHDL getting Array elements with std_logic_vector

Hello, I'm having some trouble synthesizing my code, I'm running out of logic cells on my DE2 Altera board. I want to use the values from 4 std_logic_vectors(7 downto 0) to retrieve the e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Tricky,

Currently I have part of an image stored in M4K ram that I read and process. I understand this not a good design. I do intend to ultimately store the data on external RAM. I was hoping to read the complete image into a array and process the image. As I learn more about the characteristics of the FPGA I am better understanding my limitations.

Can you please elaborate on the follow statement "your "registers" would only use 40 of the m4ks available"

Thank you for the feedback.