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Altera_Forum
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13 years ago

VHDL getting Array elements with std_logic_vector

Hello, I'm having some trouble synthesizing my code, I'm running out of logic cells on my DE2 Altera board. I want to use the values from 4 std_logic_vectors(7 downto 0) to retrieve the e...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The specs for your project are your own. As you get more experienced, it gets easier to understand how different elements work and how many resources they will use.