VHDL example of DCFIFO

I posted some VHDL FIFO simulation code in this thread a while back ...

http://www.alteraforum.com/forum/showthread.php?t=38988

Cheers,

Dave

Dave,

Thank you. dcfifo_top should be enough to get me going.

Scott

Dave,

The dcfifo is working, sort of.

lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.

The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.

Scott

Hey Scott,

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The dcfifo is working, sort of.

lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.

The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.

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Do your simulations and logic analyzer traces match?

Which version of Quartus and Modelsim are you using? The reason I initially wrote the zip file I referred you to was that I had found an issue when simulating with Modelsim-SE versus Modelsim-ASE a long time ago (many versions of Quartus ago).

If you have a Modelsim simulation that shows the issue, or the simulations I wrote show it, I can take a look. I have multiple versions of Modelsim and Quartus installed on a machine, I could see if they give different results.

Cheers,

Dave

Dave,

I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.

Scott

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Dave,

I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.

Scott

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But that doesnt tell you if you have bugs in your code, which is what modelsim will tell you.

I highly suggest you write a testbench and fire modelsim up.

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I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.

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You should be able to run the Modelsim simulations I provided, and then edit them to match your FIFO.

As Tricky comments, the idea here is to see if there is a difference between simulation and hardware, as that is indicative of a bug. If both simulation and hardware match, then there is more likely a misunderstanding in the implementation. This will also help you understand that its important to simulate before testing in hardware, since its much easier to probe all of the design signals.

Cheers,

Dave

It is not that I disagree but prior to ModelSim, SignalTap and Chipscope all there was were logic analyzers and oscilloscopes. It is amazing the complex logic I got working back then using just those archaic tools. I can watch any signal that can be routed to an I/O pin. Sometimes all I had was a counter chip to use as a divider and an LED. Had to time the blink rate before the frequency counter.

Scott

Hi Scott,

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It is not that I disagree but prior to ModelSim, SignalTap and Chipscope all there was were logic analyzers and oscilloscopes. It is amazing the complex logic I got working back then using just those archaic tools. I can watch any signal that can be routed to an I/O pin. Sometimes all I had was a counter chip to use as a divider and an LED. Had to time the blink rate before the frequency counter.

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I'm not arguing against using logic analyzers. Modelsim is just another tool. The advantage of Modelsim is that during development, you gain a high-level of confidence that your design "will just work" if you have a simulation that works in Modelsim, and you synthesize it, and it passes timing (based on TimeQuest constraints).

I very rarely have issues with hardware designs that have good simulations. One step in the debug of these failing systems is to look at the functional RTL simulation (basically the Modelsim simulation of the code), and then the post-place-and-route simulation (the Modelsim simulation of the HDL code generated by Quartus). If you see a discrepancy in those simulations relative to hardware, then you have something to work with.

Another important reason for creating a simulation is that it gives you the ability to show someone else your problem. I don't have access to your hardware, and so I cannot look at it. Sure, you can post a logic analyzer trace, but that does not really help much. If you post a simulation, then I'll be able to look at your code, along with how you use it, and see whether or not there is an invalid assumption in there.

Anyways, these are just comments :)

Did you get a chance to run the Modelsim simulations that I wrote? Do you see a difference in those waveforms relative to your logic analyzer traces?

Cheers,

Dave