VHDL example of DCFIFO

Dave,

The dcfifo is working, sort of.

lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.

The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.

Scott