VHDL example of DCFIFO

Hi Scott,

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It is not that I disagree but prior to ModelSim, SignalTap and Chipscope all there was were logic analyzers and oscilloscopes. It is amazing the complex logic I got working back then using just those archaic tools. I can watch any signal that can be routed to an I/O pin. Sometimes all I had was a counter chip to use as a divider and an LED. Had to time the blink rate before the frequency counter.

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I'm not arguing against using logic analyzers. Modelsim is just another tool. The advantage of Modelsim is that during development, you gain a high-level of confidence that your design "will just work" if you have a simulation that works in Modelsim, and you synthesize it, and it passes timing (based on TimeQuest constraints).

I very rarely have issues with hardware designs that have good simulations. One step in the debug of these failing systems is to look at the functional RTL simulation (basically the Modelsim simulation of the code), and then the post-place-and-route simulation (the Modelsim simulation of the HDL code generated by Quartus). If you see a discrepancy in those simulations relative to hardware, then you have something to work with.

Another important reason for creating a simulation is that it gives you the ability to show someone else your problem. I don't have access to your hardware, and so I cannot look at it. Sure, you can post a logic analyzer trace, but that does not really help much. If you post a simulation, then I'll be able to look at your code, along with how you use it, and see whether or not there is an invalid assumption in there.

Anyways, these are just comments :)

Did you get a chance to run the Modelsim simulations that I wrote? Do you see a difference in those waveforms relative to your logic analyzer traces?

Cheers,

Dave