VHDL example of DCFIFO

Hey Scott,

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The dcfifo is working, sort of.

lpm_showahead => "ON" but the data coming out is delayed by one read cycle no matter how many write or read clock cycles the rdreq occurs after the wrreq. If showahead is turn off the data coming out is delayed by two clock cycles. This has been verified using an external logic analyzer watching the input and output data along with the clocks and read and write requests.

The aclr line also doesn't seem to actually clear the fifo. read_aclr_synch and write_aclr_synch are both on.

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Do your simulations and logic analyzer traces match?

Which version of Quartus and Modelsim are you using? The reason I initially wrote the zip file I referred you to was that I had found an issue when simulating with Modelsim-SE versus Modelsim-ASE a long time ago (many versions of Quartus ago).

If you have a Modelsim simulation that shows the issue, or the simulations I wrote show it, I can take a look. I have multiple versions of Modelsim and Quartus installed on a machine, I could see if they give different results.

Cheers,

Dave