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I have not figured out how to use Modelsim yet so all I have is the logic analyzer output which, in the end, is what is really happening.
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You should be able to run the Modelsim simulations I provided, and then edit them to match your FIFO.
As Tricky comments, the idea here is to see if there is a difference between simulation and hardware, as that is indicative of a bug. If both simulation and hardware match, then there is more likely a misunderstanding in the implementation. This will also help you understand that its important to simulate before testing in hardware, since its much easier to probe all of the design signals.
Cheers,
Dave
Honored Contributor
