VHDL Configuration for TestBenches Issue

Hello,

I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit.

I also have a testbench with two architecture (named test1, test2) , set for ModelSim-Altera simulator.

Finally, I have a configuration declaration at the testbench file unit..

I was wonder why simulator always executes the last architecture described (named "test2") instead of executing what is indicated in the configuration declaration.

Someone of you can help me?

Thanks.

---------------------------------------------------------
entity TestBench is
end entity TestBench;
---------------------------------------------------------
architecture test1 of TestBench is
component device1 is
port (x, y : in STD_LOGIC; z: out STD_LOGIC);
end component device1;
begin
gateTst1: device1 port map (x => a, y => b, z => c);
...
end architecture test1;
---------------------------------------------------------
architecture test2 of TestBench is
component device2 is
port (x, y : in STD_LOGIC; z: out STD_LOGIC);
end component device2;
begin
gateTst2: device2 port map (x => a, y => b, z => c);
...
end architecture test2;
-------------------------------------------------------
configuration Tester of TestBench is
for io
for gateTst1 : device1
use entity WORK.myAnd2(ex1)
port map (x => a, y => b, z => c);
end for;
end for;
end configuration Tester;
---------------------------------------------------------