Forum Discussion

emaferna's avatar
emaferna
Icon for New Contributor rankNew Contributor
5 years ago

VHDL Configuration for TestBenches Issue

Hello, I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit. I also have a testbench with two architecture (named test1, test...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Emanuele,


I agree with you Quartus behaves weirdly when doing configuration simulation. As a workaround, I suggest you to simulate the configuration from Modelsim instead of Quartus and I believe that is the only way to do it for now


Thanks,

Regards