VHDL Configuration for TestBenches Issue

Hi,

Thanks for the reply.

What I tried to do was to run the testbench by setting up the mytestbench.vhd file in Quartus: Setting -> Simulation -> Compile test bench ...

In this way the simulation started but ModelSim ignored the configuration declaration present in the file mytestbench.vhd; to run the simulation on the configuration I should:

1) stop the simulation that has opened

2) go to the configuration design unit, in the Library tab,

3) right-click on it and launch the simulation (it seems to me that it is also the equivalent of the command you gave me).

4) then see the signals of interest

The point is that I tried from within Quartus but I failed, as ModelSim seems to implement the default binding on the testbench it reads from Quartus anyway.

So I also tried to comment out the configuration declaration in the mytestbench.vhd file and create a new file containing only the configuration declaration, mytestconfig.vhd, (leaving untouched the mytestbench.vhd file in the same folder), and thus put the file mytestconfig.vhd in Quartus: Setting -> Simulation -> Compile test bench ...

However, when running the simulation, the simulator gave me an error.

It seems that in order to simulate a configuration you have to do it from ModelSim, as indicated previously.

I wonder if, acting from inside Quartus, it is possible to choose the configuration to simulate.

Thank you.