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emaferna's avatar
emaferna
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5 years ago

VHDL Configuration for TestBenches Issue

Hello, I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit. I also have a testbench with two architecture (named test1, test...
emaferna's avatar
emaferna
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5 years ago

Sorry, I did a syntax error in the previus post: the architecture in the configuration is test1.

This error was made only in writing the post, not in the running vhdl code.

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configuration Tester of TestBench is
for test1
for gateTst1 : device1
use entity WORK.myAnd2(ex1)
port map (x => a, y => b, z => c);
end for;
end for;
end configuration Tester;
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