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emaferna's avatar
emaferna
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5 years ago

VHDL Configuration for TestBenches Issue

Hello, I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit. I also have a testbench with two architecture (named test1, test...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Emanuele,


I am not sure how did you start the simulation but, to simulate configuration, you have to start the simulation with the configuration as the top module. The simulator will load the entity/architecture pair according to the code in configuration block. Like this:


vsim work.Tester; run


Thanks,

Regards