Honored ContributorHi guys, I'm new here. What would be the VDHL code for this Mealy machine? Thanks
A sequential circuit with two Dflip-flops Aand B, two inputs, xand y; and one output z specified by the following next-state and output equations. A(t +1)=xy’ +xB B(t +1)=xA+xb’ z=A
Honored ContributorWhy not show the code you've written and what problems you're having
Honored Contributorlibrary ieee;
use ieee.std_logic_1164.all; entity lab2exercise2 is port ( clk : in std_logic; data_in1 : in std_logic; data_in2 : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); end lab2exercise2; architecture rtl of lab2exercise2 is -- Build an enumerated type for the state machine type state_type is (a, b, c, d); -- Register to hold the current state signal state : state_type; signal clk_1hz : std_logic:= '0'; begin process(clk) variable counter : integer := 0; variable edge_toggle : std_logic := '0'; begin if (rising_edge(clk)) then counter := counter + 1; if (counter = 25000000) then edge_toggle := not edge_toggle; counter := 0; end if; end if; clk_1hz <= edge_toggle; end process; process (clk_1hz, reset) begin if reset = '1' then state<= a; elsif (rising_edge(clk_1hz)) then -- Determine the next state synchronously, based on -- the current state and the input case state is when a=> if((data_in1 = '0') & (data_in2 = '0'))then state<=a; if((data_in1 = '1') & (data_in2 = '0'))then state<=a; if((data_in1 = '1') & (data_in2 = '1')) then state<=a; else state<=c; end if; when b=> if ((data_in1 = '0') & (data_in2 = '0')) then state<=a; else if ((data_in1 = '1') & (data_in2 = '0'))then state<=d; else if ((data_in1 = '1') & (data_in2 = '1'))then state<=d; else state<=c; end if; when c=> if ((data_in1 = '1') & (data_in2 = '0')) then state<=a; else if ((data_in1 = '1') & (data_in2 = '1')) then state<=a; else if ((data_in1 = '0') & (data_in2 = '1')) then state<=d; else state<=b; end if; when d=> if ((data_in1 = '0') & (data_in2 = '1'))then state<=d; else if((data_in1 = '1') & (data_in2 = '0')) then state<=d; else if((data_in1 = '1') & (data_in2 = '1')) then state<=d; else state<=b; end if; end case; end if; end process; -- Determine the output based only on the current state -- and the input (do not wait for a clock edge). process (state, data_in1, data_in2) begin case state is when a=> if((data_in1 = '0') & (data_in2 = '0'))then data_out<= "000"; if((data_in1 = '1') & (data_in2 = '0'))then data_out<= "000"; if((data_in1 = '1') & (data_in2 = '1')) then data_out<= "000"; else data_out<= "010"; end if; when b=> if ((data_in1 = '0') & (data_in2 = '0')) then data_out<= "000"; else if ((data_in1 = '1') & (data_in2 = '0'))then data_out<= "011"; else if ((data_in1 = '1') & (data_in2 = '1'))then data_out<= "011"; else data_out<= "010"; end if; when c=> if ((data_in1 = '1') & (data_in2 = '0')) then data_out<= "100"; else if ((data_in1 = '1') & (data_in2 = '1')) then data_out<= "100"; else if ((data_in1 = '0') & (data_in2 = '1')) then data_out<= "111"; else data_out<= "101"; end if; when d=> if ((data_in1 = '0') & (data_in2 = '1'))then data_out<= "111"; else if((data_in1 = '1') & (data_in2 = '0')) then data_out<= "111"; else if((data_in1 = '1') & (data_in2 = '1')) then data_out<= "111"; else data_out<= "111"; end if; end case; end process; end rtl; This is my code. I tried running it but I always get error 10500 at lines "when b=>, when c=> and when d=>" and "end processes".Honored ContributorHi,
1. It`s syntax error about If statement, follow below syntax,if condition1 then
target := expression1;
elsif condition2 then
target := expression2;
·
·
·
elsif conditionN-1 then
target := expressionN-1;
else
target := expressionN;
end if;Already edited the code but i still get errors at when b=>, when c=> and when d=>" and "end processes".
All of the errors are 10500 VHDL Syntax error at near text "when"; expecting "if", identifier, etc...sorry couldn't really recall it.Honored ContributorHi,
I would suggest go through the VHDL Basic online training, https://www.altera.com/support/training/course/ohdl1110.html check modified code,library ieee;
use ieee.std_logic_1164.all;
entity lab2exercise2 is
port
(
clk : in std_logic;
data_in1 : in std_logic;
data_in2 : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 downto 0)
);
end lab2exercise2;
architecture rtl of lab2exercise2 is
-- Build an enumerated type for the state machine
type state_type is (a, b, c, d);
-- Register to hold the current state
signal state : state_type;
signal clk_1hz : std_logic:= '0';
begin
process(clk)
variable counter : integer := 0;
variable edge_toggle : std_logic := '0';
begin
if (rising_edge(clk)) then
counter := counter + 1;
if (counter = 25000000) then
edge_toggle := not edge_toggle;
counter := 0;
end if;
end if;
clk_1hz <= edge_toggle;
end process;
process (clk_1hz, reset)
begin
if reset = '1' then
state<= a;
elsif (rising_edge(clk_1hz)) then
-- Determine the next state synchronously, based on
-- the current state and the input
case state is
when a=>
if((data_in1 = '0') and (data_in2 = '0'))then
state<=a;
elsif((data_in1 = '1') and (data_in2 = '0'))then
state<=a;
elsif((data_in1 = '1') and (data_in2 = '1')) then
state<=a;
else
state<=c;
end if;
when b=>
if ((data_in1 = '0') and (data_in2 = '0')) then
state<=a;
elsif ((data_in1 = '1') and (data_in2 = '0'))then
state<=d;
elsif ((data_in1 = '1') and (data_in2 = '1'))then
state<=d;
else
state<=c;
end if;
when c=>
if ((data_in1 = '1') and (data_in2 = '0')) then
state<=a;
elsif ((data_in1 = '1') and (data_in2 = '1')) then
state<=a;
elsif ((data_in1 = '0') and (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
when d=>
if ((data_in1 = '0') and (data_in2 = '1'))then
state<=d;
elsif((data_in1 = '1') and (data_in2 = '0')) then
state<=d;
elsif((data_in1 = '1') and (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
end case;
end if;
end process;
-- Determine the output based only on the current state
-- and the input (do not wait for a clock edge).
process (state, data_in1, data_in2)
begin
case state is
when a=>
if((data_in1 = '0') and (data_in2 = '0'))then
data_out<= "00";
elsif((data_in1 = '1') and (data_in2 = '0'))then
data_out<= "00";
elsif((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "00";
else
data_out<= "01";
end if;
when b=>
if ((data_in1 = '0') and (data_in2 = '0')) then
data_out<= "00";
elsif ((data_in1 = '1') and (data_in2 = '0'))then
data_out<= "11";
elsif ((data_in1 = '1') and (data_in2 = '1'))then
data_out<= "11";
else
data_out<= "10";
end if;
when c=>
if ((data_in1 = '1') and (data_in2 = '0')) then
data_out<= "10";
elsif ((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "10";
elsif ((data_in1 = '0') and (data_in2 = '1')) then
data_out<= "11";
else
data_out<= "10";
end if;
when d=>
if ((data_in1 = '0') and (data_in2 = '1'))then
data_out<= "11";
elsif((data_in1 = '1') and (data_in2 = '0')) then
data_out<= "11";
elsif((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "11";
else
data_out<= "11";
end if;
end case;
end process;
end rtl;in VHDL, & is the concatenate operator, not the "and" operator.
You need to replace all & with andHonored ContributorHi,
Have you resolved the issue? Do you need further assistance? Best Regards Vikas Jathar (This message was posted on behalf of Intel Corporation)
Frequent ContributorHere's the corrected code.. see if you can find out your basic mistakes.. This one compiles without any issues.
library ieee;
use ieee.std_logic_1164.all;
entity lab2exercise2 is
port (
clk : in std_logic;
data_in1 : in std_logic;
data_in2 : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(2 downto 0)
);
end lab2exercise2;
architecture rtl of lab2exercise2 is
-- Build an enumerated type for the state machine
type state_type is (a, b, c, d);
-- Register to hold the current state
signal state : state_type;
signal clk_1hz : std_logic:= '0';
begin
process(clk)
variable counter : integer := 0;
variable edge_toggle : std_logic := '0';
begin
if (rising_edge(clk)) then
counter := counter + 1;
if (counter = 25000000) then
edge_toggle := not edge_toggle;
counter := 0;
end if;
end if;
clk_1hz <= edge_toggle;
end process;
process (clk_1hz, reset)
begin
if reset = '1' then
state<= a;
elsif (rising_edge(clk_1hz)) then
-- Determine the next state synchronously, based on
-- the current state and the input
case state is
when a=>
if((data_in1 = '0') and (data_in2 = '0'))then
state<=a;
elsif(data_in1 = '1' and data_in2 = '0')then
state<=a;
elsif((data_in1 = '1') and (data_in2 = '1')) then
state<=a;
else
state<=c;
end if;
when b=>
if ((data_in1 = '0') and (data_in2 = '0')) then
state<=a;
elsif ((data_in1 = '1') and (data_in2 = '0'))then
state<=d;
elsif ((data_in1 = '1') and (data_in2 = '1'))then
state<=d;
else
state<=c;
end if;
when c=>
if ((data_in1 = '1') and (data_in2 = '0')) then
state<=a;
elsif ((data_in1 = '1') and (data_in2 = '1')) then
state<=a;
elsif ((data_in1 = '0') and (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
when d=>
if ((data_in1 = '0') and (data_in2 = '1'))then
state<=d;
elsif((data_in1 = '1') and (data_in2 = '0')) then
state<=d;
elsif((data_in1 = '1') and (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
end case;
end if;
end process;
-- Determine the output based only on the current state
-- and the input (do not wait for a clock edge).
process (state, data_in1, data_in2)
begin
case state is
when a=>
if((data_in1 = '0') and (data_in2 = '0'))then
data_out<= "000";
elsif((data_in1 = '1') and (data_in2 = '0'))then
data_out<= "000";
elsif((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "000";
else
data_out<= "010";
end if;
when b=>
if ((data_in1 = '0') and (data_in2 = '0')) then
data_out<= "000";
elsif ((data_in1 = '1') and (data_in2 = '0'))then
data_out<= "011";
elsif ((data_in1 = '1') and (data_in2 = '1'))then
data_out<= "011";
else
data_out<= "010";
end if;
when c=>
if ((data_in1 = '1') and (data_in2 = '0')) then
data_out<= "100";
elsif ((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "100";
elsif ((data_in1 = '0') and (data_in2 = '1')) then
data_out<= "111";
else
data_out<= "101";
end if;
when d=>
if ((data_in1 = '0') and (data_in2 = '1'))then
data_out<= "111";
elsif((data_in1 = '1') and (data_in2 = '0')) then
data_out<= "111";
elsif((data_in1 = '1') and (data_in2 = '1')) then
data_out<= "111";
else
data_out<= "111";
end if;
end case;
end process;
end rtl; 
