Verilog real functions and compile time

Taking a more real scenario, lets say I want to make a LUT of fixed-point values representing 1/sqrt(x). Finding sqrt(x) is as easy as raising x^0.5. Raising x^0.5 is done by using exp(0.5 * ln(x)) - each of which should not lose precision by truncating and rounding for every return.

In the end, while the code you provided does work for trivial cases (which I had asked about), once the LUT gets a little more complicated, it all seems to fall apart.

The conclusion is that Quartus II does not support functions that return real types, even if they are only evaluated at compile time, which is a shame.

I think the Quartus error message help really says it all here!

Error (10172): Verilog HDL unsupported feature error at x.v(6): real variable data type values are not supported

Verilog HDL unsupported feature error at <location>: real variable data type values are not supported

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CAUSE: In a Verilog Design File (.v) at the specified location, you declared a real variable data type. although verilog hdl supports real variable data types, this type is not supported in the quartus ii software.

ACTION: Change the data type of the variable to something other than real.

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I think the Quartus error message help really says it all here!

Error (10172): Verilog HDL unsupported feature error at x.v(6): real variable data type values are not supported

Verilog HDL unsupported feature error at <location>: real variable data type values are not supported

--------------------------------------------------------------------------------

CAUSE: In a Verilog Design File (.v) at the specified location, you declared a real variable data type. although verilog hdl supports real variable data types, this type is not supported in the quartus ii software.

ACTION: Change the data type of the variable to something other than real.

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If the function were used after compilation time and active in the design itself, then I would understand Quartus II getting upset - but the fact of the matter is that each real function call I perform gets collapsed down to a constant, static value. In other words, to allow for reusable code and a greater number of built-time parameters, I want to use Quartus II as a fancy calculator. It is obviously capable of performing operations (at compile time) on real numbers. Quartus II should error only if:

- Non-static real values are being evaluated by a function

- A real is declared as a port input or output

Otherwise, it's just a macro - right? Even if you assign a real value to an array of wires, Verilog isn't strictly typed so it should just perform the conversion - right?

I see exactly what you are trying to do and agree that it seems reasonable to assume that Quartus should be able to reduce your functions at compile time.

However, it doesn't support it....yet! So probably time to move on and solve the problem in another way. :rolleyes:

The missing support of real data type is common to a number of Verilog synthesis tools, not just special to Quartus. The structural differences between the languages may be reason, I don't know exactly. I'm also not sure, if the extensive support of real compile-time operations in Quartus VHDL exists in other synthesis tools, at least real is marked as unsupported e.g in the Synopsis VHDL reference manual.

But also the Quartus compile time features for VHDL aren't documented in detail, you have to find out by yourself. Personally I'm happy with my favourite VHDL language, a colleague who generally prefers Verilog has started to use mixed language designs with VHDL components for special purposes.

Even if Quartus systhesis would support the real data type completety it would not help Bpadalino to do what he wants to. Verilog itself supports only a few operators for the real data type. Definitely no sqrt, exp or ln.

Bpadalino, my recommndation for you: Use a memory module and initialize is with a hex file. Generate the hex file with a simpe C programm that calculates the data. Verilog isn't made for this stuff.

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Even if Quartus systhesis would support the real data type completety it would not help Bpadalino to do what he wants to. Verilog itself supports only a few operators for the real data type. Definitely no sqrt, exp or ln.

Bpadalino, my recommndation for you: Use a memory module and initialize is with a hex file. Generate the hex file with a simpe C programm that calculates the data. Verilog isn't made for this stuff.

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I wrote said functions in Verilog to have something similar to ieee.math_real, except to be in Verilog. I was quite disappointed when those functions were only useful for simulation.

I really am just trying to avoid using C, Perl, Python, or any other external programming language to complicate matters even more.

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Or use a VHDL component, if you want to have all calculations inside the Quartus project.

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I'd prefer to stay away from mixed-mode HDL, and oftentimes it isn't an option (for me) to mix.

I really wanted to try to be as language agnostic as possible, but it seems I'll stick with VHDL as my language preference. For my purposes, it seems that Verilog is just too limited.

you should file an enhancement request with Altera.

that said after i started using HDL only to describe hardware and not using it as a scripting language i became much happier. not an ideal solution, but...