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Honored Contributor
Honored ContributorVerilog real functions and compile time
I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_ForumHonored Contributor
Honored Contributoryou should file an enhancement request with Altera.
that said after i started using HDL only to describe hardware and not using it as a scripting language i became much happier. not an ideal solution, but...