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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

you should file an enhancement request with Altera.

that said after i started using HDL only to describe hardware and not using it as a scripting language i became much happier. not an ideal solution, but...