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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I see exactly what you are trying to do and agree that it seems reasonable to assume that Quartus should be able to reduce your functions at compile time.

However, it doesn't support it....yet! So probably time to move on and solve the problem in another way. :rolleyes: