Verilog real functions and compile time

The missing support of real data type is common to a number of Verilog synthesis tools, not just special to Quartus. The structural differences between the languages may be reason, I don't know exactly. I'm also not sure, if the extensive support of real compile-time operations in Quartus VHDL exists in other synthesis tools, at least real is marked as unsupported e.g in the Synopsis VHDL reference manual.

But also the Quartus compile time features for VHDL aren't documented in detail, you have to find out by yourself. Personally I'm happy with my favourite VHDL language, a colleague who generally prefers Verilog has started to use mixed language designs with VHDL components for special purposes.