Verilog if statement with a signed signal

Oh, should also say (in case it makes a difference) that this is Quartus Prime Pro 16.1, compiling for SystemVerilog, running on Windows 10.

Andy

With only a snippet, cant really comment.

Can you post more code?

That may be coz you've used integer values in the if statement. When you use integers, Quartus will treat it as unsigned 32 bit integers during synthesis and truncate the unused bits. I say try specifying the bit values in the if condition

if ( signal < 4'b0000)

else

...

Using the signed values for comparison will or should yield the correct results.

I'm not sure that that would help though - my understanding was that int 0 is effectively the same as 32'd0, no? So surely a comparison to 0 or a comparison to 4'b0000 would behave in the same way?

​Try this:

module test
(
	input signed [3:0] a,
	output eq,
	output gt,
	output lt
);
 
localparam x = 4'sb1101; // neg 3
 
assign eq = (a == x) ? 1'b1:1'b0;
assign gt = (a > x) ? 1'b1:1'b0;
assign lt = (a < x) ? 1'b1:1'b0;
 
endmodule

Just to be clear - I'm really not actually looking for a fix to the code (I've done that by just manually doing a check on the sign bit). I'm just very confused why the Quartus compiler is doing something fundamentally different than the Modelsim compiler. Obviously one of them is doing the correct thing and the other isn't....