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AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

Verilog if statement with a signed signal

This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form: typedef...
  • AndyN's avatar
    AndyN
    7 years ago

    So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....

bitwise's avatar
bitwise
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

​Try this:

module test
(
	input signed [3:0] a,
	output eq,
	output gt,
	output lt
);
 
localparam x = 4'sb1101; // neg 3
 
assign eq = (a == x) ? 1'b1:1'b0;
assign gt = (a > x) ? 1'b1:1'b0;
assign lt = (a < x) ? 1'b1:1'b0;
 
endmodule