Forum Discussion
AndyN
Occasional Contributor
Occasional ContributorVerilog if statement with a signed signal
This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form: typedef...
So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....
bitwiseOccasional Contributor
Occasional ContributorTry this:
module test
(
input signed [3:0] a,
output eq,
output gt,
output lt
);
localparam x = 4'sb1101; // neg 3
assign eq = (a == x) ? 1'b1:1'b0;
assign gt = (a > x) ? 1'b1:1'b0;
assign lt = (a < x) ? 1'b1:1'b0;
endmodule
