Forum Discussion
AndyN
Occasional Contributor
Occasional ContributorVerilog if statement with a signed signal
This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form: typedef...
So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....
AndyNOccasional Contributor
Occasional ContributorI'm not sure that that would help though - my understanding was that int 0 is effectively the same as 32'd0, no? So surely a comparison to 0 or a comparison to 4'b0000 would behave in the same way?
