Forum Discussion
AndyN
Occasional Contributor
Occasional ContributorVerilog if statement with a signed signal
This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form: typedef...
So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....
Abe
Frequent Contributor
Frequent ContributorThat may be coz you've used integer values in the if statement. When you use integers, Quartus will treat it as unsigned 32 bit integers during synthesis and truncate the unused bits. I say try specifying the bit values in the if condition
if ( signal < 4'b0000)
else
...
Using the signed values for comparison will or should yield the correct results.
