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AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
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Verilog if statement with a signed signal

This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form: typedef...
  • AndyN's avatar
    AndyN
    7 years ago

    So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....

AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Just to be clear - I'm really not actually looking for a fix to the code (I've done that by just manually doing a check on the sign bit). I'm just very confused why the Quartus compiler is doing something fundamentally different than the Modelsim compiler. Obviously one of them is doing the correct thing and the other isn't....