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Altera_Forum
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17 years ago

Unable to place RAM cells in design

Hi folks,

I'm trying to work on an SoPC design. I've used my architecture as an IP and inserted it onto the SoPC having Nios II CPU, jtag-uart, interval timer, on chip memory, and a pio.

I'm trying to fit this device onto a Cyclone II EP2C20F484C7.

My IP's architecture uses DPRAM cells, around 32 of them with a depth of 150 bits each accessed 1 bit at a time. So the total usage during its compilation was ~ 4096 memory bits.

Now, after generating an SoPC, when i try to compile it, i get the following error:

Error: Cannot place 265 RAM cells or portions of RAM cells in design.

Please advice me as to what I should be doing.

btw, I'm an amateur as far as the quartus tool and SoPC are concerned.

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  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Apparently, the problem isn't related to the said 32x150 bits DP rather than SOPC memory. The memory requirement is doubled by the Quartus software to fix a Cyclone II silicon bug. This workaround may be unneccessary in some cases and can be disabled then, see the Cyclone II Errata Sheet for details. As a first step, I would reduce SOPC memory until the design fits.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi there,

    I'm not able to run (build) even a simple Hello world program in Nios IDE, since it says the required memory is far more than that provided:

    onchip_mem is full (hello_world_3.elf section .text). region needs to be 25984 bytes larger.

    Now, when I add 26k to the onchip memory, the design does not fit on the board.

    Please suggest me as to what I should do!

    btw, this is the resource usage summary

    --- Quote Start ---

    Total logic elements 3,526 / 18,752 ( 19 % )

    -- Combinational with no register 1571

    -- Register only 329

    -- Combinational with a register 1626

    Logic element usage by number of LUT inputs

    -- 4 input functions 1219

    -- 3 input functions 1167

    -- <=2 input functions 811

    -- Register only 329

    Logic elements by mode

    -- normal mode 2551

    -- arithmetic mode 646

    Total registers* 1,955 / 19,649 ( 10 % )

    -- Dedicated logic registers 1,955 / 18,752 ( 10 % )

    -- I/O registers 0 / 897 ( 0 % )

    Total LABs: partially or completely used 279 / 1,172 ( 24 % )

    User inserted logic elements 0

    Virtual pins 0

    I/O pins 22 / 315 ( 7 % )

    -- Clock pins 1 / 8 ( 13 % )

    Global signals 14

    M4Ks 48 / 52 ( 92 % )

    Total memory bits 178,880 / 239,616 ( 75 % )

    Total RAM block bits 221,184 / 239,616 ( 92 % )

    Embedded Multiplier 9-bit elements 0 / 52 ( 0 % )

    PLLs 0 / 4 ( 0 % )

    Global clocks 14 / 16 ( 88 % )

    Average interconnect usage 7%

    Peak interconnect usage 19%

    Maximum fan-out node clk~clkctrl

    Maximum fan-out 1714

    Highest non-global fan-out signal quad_sys:quad|quad16_0:the_quad16_0|quad16:the_quad16|nlfsr10:nlfsr_10|wradd[4]~731

    Highest non-global fan-out 520

    Total fan-out 17597

    Average fan-out 3.17

    --- Quote End ---

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Try to uncheck the option "auto ram replacement" under "assignments -> device -> analysis & synthesis settings"

    It would probably help more if you included the summary of the compilation of the SOPC system not just the ip. In the compilation report there is a section called "fitter -> resource usage -> resource utilization by entity" where you can check exactly which resources every component uses. That can maybe help you to find your problem area.

    //Ola
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I already mentioned, that the doubled RAM block requirement is due to a Quartus workround for a silicon bug. However, with Rev. B and later devices the cycloneii_safe_write parameter can be changed from default restructure to verified_safe to double the block count available for dual port RAM.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I included an SRAM in the SOPC builder and now the problem does not persist.

    The next hurdle is programming the SoPC. How do i go about programming the Nios II processor to interact with my IP?