Unable to place RAM cells in design

Hi there,

I'm not able to run (build) even a simple Hello world program in Nios IDE, since it says the required memory is far more than that provided:

onchip_mem is full (hello_world_3.elf section .text). region needs to be 25984 bytes larger.

Now, when I add 26k to the onchip memory, the design does not fit on the board.

Please suggest me as to what I should do!

btw, this is the resource usage summary

--- Quote Start ---

Total logic elements 3,526 / 18,752 ( 19 % )

-- Combinational with no register 1571

-- Register only 329

-- Combinational with a register 1626

Logic element usage by number of LUT inputs

-- 4 input functions 1219

-- 3 input functions 1167

-- <=2 input functions 811

-- Register only 329

Logic elements by mode

-- normal mode 2551

-- arithmetic mode 646

Total registers* 1,955 / 19,649 ( 10 % )

-- Dedicated logic registers 1,955 / 18,752 ( 10 % )

-- I/O registers 0 / 897 ( 0 % )

Total LABs: partially or completely used 279 / 1,172 ( 24 % )

User inserted logic elements 0

Virtual pins 0

I/O pins 22 / 315 ( 7 % )

-- Clock pins 1 / 8 ( 13 % )

Global signals 14

M4Ks 48 / 52 ( 92 % )

Total memory bits 178,880 / 239,616 ( 75 % )

Total RAM block bits 221,184 / 239,616 ( 92 % )

Embedded Multiplier 9-bit elements 0 / 52 ( 0 % )

PLLs 0 / 4 ( 0 % )

Global clocks 14 / 16 ( 88 % )

Average interconnect usage 7%

Peak interconnect usage 19%

Maximum fan-out node clk~clkctrl

Maximum fan-out 1714

Highest non-global fan-out signal quad_sys:quad|quad16_0:the_quad16_0|quad16:the_quad16|nlfsr10:nlfsr_10|wradd[4]~731

Highest non-global fan-out 520

Total fan-out 17597

Average fan-out 3.17

--- Quote End ---

Thank you!