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Altera_Forum
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17 years ago

Unable to place RAM cells in design

Hi folks, I'm trying to work on an SoPC design. I've used my architecture as an IP and inserted it onto the SoPC having Nios II CPU, jtag-uart, interval timer, on chip memory, and a pio. I'm try...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Apparently, the problem isn't related to the said 32x150 bits DP rather than SOPC memory. The memory requirement is doubled by the Quartus software to fix a Cyclone II silicon bug. This workaround may be unneccessary in some cases and can be disabled then, see the Cyclone II Errata Sheet for details. As a first step, I would reduce SOPC memory until the design fits.