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Altera_Forum
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17 years ago

Unable to place RAM cells in design

Hi folks, I'm trying to work on an SoPC design. I've used my architecture as an IP and inserted it onto the SoPC having Nios II CPU, jtag-uart, interval timer, on chip memory, and a pio. I'm try...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I already mentioned, that the doubled RAM block requirement is due to a Quartus workround for a silicon bug. However, with Rev. B and later devices the cycloneii_safe_write parameter can be changed from default restructure to verified_safe to double the block count available for dual port RAM.