UART and MODELSIM ALTERA (code attached)

Well, for a start, the RX.vhd has code in parrellel to the clock - this is bad practice, it should be in it's own asynchronous process.

This async code contains a counter - with asynchronous counters you're just putting the code into an infinite loop - as soon as the counter increments, it will increment again over and over in 0 time, hence you will lock up the simulator. If you insist on doing a counter in an asynchronous process, you should produce a count_next signal and then register it in another process.

You have an almost identical problem in tx.vhd.

Inside a synchronous process, you only need to have the clock and any asynchronous resets in the sensitivity list. A sensitivity list tells the process which signals should cause a re-evaluation of the process. So for a synchronous process, the outputs can only change on a clock edge, so its not worth having other signals in there as nothing will change when they change.

Hi friends, I have just a theoretical doubt about rx uart and I would appreciate if any help.

The system clock, provided for the board is 50Mhz, and I was needing a 115200bps UART.

I made a mod entity that outputs 1 tick every 13 ticks from the system clock including a 16 oversampling, based on this claculations:

16 is my choice for the number of oversampling for RX bits.

115200bps is the uart baud rate.

50Mhz is the system clock.

50Mhz/(16*115200) = 27,126736111 what I assumed to be 27.

So, if 50Mhz system clock has 20 ps in each cicle, after 27*20ps = 540 ps the mod entity would be generate one tick.

As soon as the start bit is detected, I am interested in sampling the middle of this bit, so, at 13ª cicle or 540ps/2 = 270 ps after this start bit is being detected.

All this explanation is to justify why I made the mod count from 0 to 12 to outputs one tick, for detecting the middle of start bit and after I wait two ticks of 0 to 12, I take the sample for data bits and stop bits.

It gives me a conversion from 50Mhz to 1/540ps = 1.851 Hz, what I think it is close to the1.8432Hz needed to 115200bps.

I attached the begin and the end of simulation.

Are that correct?

Thank you very much.

Hi,

I have a very simple issue, could some one give me a help with that please?

I made a counter from 0 to 12 to aproximate a counting from 0 to 12,5 need to make a 115200 bps rx uart.

This counting should begin when the rx receives the start bit '0', and reset when the stop bit' 1' is achieved.

So, the RX controls the reset of the MOD counter. I made this way to avoid the pulse going over the length of the bit for the next bytes, due to the error 0,5 in counting.

the only signal I need help in the code is in rx_uart.vhd.vhd , signal en_mod_reset: std_logic:='1';

when it is '1', the mod_27_uart.vhd do not count. When it is '0', it starts to count.

It works in the first byte received, but after it goes '1' forever.

I know it is about semantic, but I cant see what is my falt in the code.

Thanks.

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according to the code you posted, en_mod_reset doesnt connect to anything...

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Sorry I did not make it clear enough.

Assume that en_mod, associated to the signal en_mod_reset in uart_rx, is connected to the reset in the mod_27.

Both of them are connected to the 50MHz clock and were simulated. The circuit is working normally if I connect the reset of the mod_27 to the reset of the whole system.

But i need the mod_27 reseted if no start bit in uart_rx is detected. So uart_rx controls the mod_27 reset trhough the en_mod_pin.

uart_rx(en_mod) -> mod_27(reset)

Thank you for your help.

In resume, why the en_mod is not changing again to '0' in uart_rx when the start bit is detected ?

case state_reg is

when idle =>

if (rx = '0') then

state_next <= start;

en_mod_reset <= '0'; -- mod 27 set, counting.

s_next <= (others => '0');

end if;

Thanks.

I'll try to model like others signal in the code. I mean like flip-flops.

If not work maybe putting the '0' or '1' directly in the output pin to try to avoid this issue.

God, You told me it a lot and I again forgot to put what is needed inside the sensitive list. I made this correction and

I made the n_mod as a flipflop model like the others signals. It works now, thank you very much Tricky. Code attached.

Hi Tricky.

All the simulations went well. I attached all the code in the case someone wants try it too:

UART.vhd is the main.

FIFO_mf.vhd is the FIFO mega function, 16 bytes.

rx_uart.vhd is the rx 115200 bps.

mod_27_uart.vhd is the modulator from 50MHz (DE2-70) to 1.84KHz (UART).

I have a altera board DE2-70 which I will load the code (UART.vhd is the main) after compilation.

UART.vhd will give me this in/outputs:

ENTITY UART IS

PORT

(

rst : IN STD_LOGIC; -- whole system reset.

serial_rx : IN STD_LOGIC; -- the data being received serially.

clock_50MHz : IN STD_LOGIC; -- whole system clock.

rd : IN STD_LOGIC; -- FIFO outputs the first byte saved from UART when it is '1'.

full : OUT STD_LOGIC; -- when FIFO is full.

empty : OUT STD_LOGIC; -- when FIFO is empty.

mod_27_cnt : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- 1.8KHz uart (115200 bps).

parallel_rx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- parallel rx from uart_rx to FIFO_mf.

usedw_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- just a counter of FIFO.

);

END UART;

I used the Quartus II to associate those pins above from UART to the FPGA:

rst is a switch on the board.

serial_rx is the serial rx on the board DE2-70.

clock_50MHz is the 50MHz clock from the board..

rd is a button fr mthe board.

full is a red led from the board.

empty another red led.

mod_27_cnt not associated, it is just for simulation visualization.

parallel_rx is associated to 8 green LEDs .

usedw_out not associated, it is just for simulation visualization.

After load the code to the board, I opened the terminal (I use one from arduino app) and reset the switch (rst) on the board.

After, for testing, I write 1 on the terminal, then 2, then 3.

Then, I pressed the button (rd) and nothing happens.

The green leds would expected to be flashing the 1 binary at first press. Then the 2 binary after second pressing. The same with 3 binary.

It happens in the simulation with ModelSim Altera.

As I am a newbie with FPGA, I would expect the simulations, as soon as they are synthesizable, happens in the board too.

I attached the schematic from qartus II to help to visualize it.

All the role are played (I think it is) by the mod_27_uart, that starts to count from 0 to 12 (ignore the 14 in the image, I correct it) to detect the start bit, and from 0 to 12 twice to detect each of the 8 data bits, and finally to 0 to 12 to detect the end bit. The mod_27_uart only starts to cout when the start bits on uart_rx is detected, so it is why the uart_rx controls the reset of the mod_27_uart.

Please could some experienced help me with this issue?

I appreciate your help.