UART and MODELSIM ALTERA (code attached)

Hi Tricky.

All the simulations went well. I attached all the code in the case someone wants try it too:

UART.vhd is the main.

FIFO_mf.vhd is the FIFO mega function, 16 bytes.

rx_uart.vhd is the rx 115200 bps.

mod_27_uart.vhd is the modulator from 50MHz (DE2-70) to 1.84KHz (UART).

I have a altera board DE2-70 which I will load the code (UART.vhd is the main) after compilation.

UART.vhd will give me this in/outputs:

ENTITY UART IS

PORT

(

rst : IN STD_LOGIC; -- whole system reset.

serial_rx : IN STD_LOGIC; -- the data being received serially.

clock_50MHz : IN STD_LOGIC; -- whole system clock.

rd : IN STD_LOGIC; -- FIFO outputs the first byte saved from UART when it is '1'.

full : OUT STD_LOGIC; -- when FIFO is full.

empty : OUT STD_LOGIC; -- when FIFO is empty.

mod_27_cnt : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- 1.8KHz uart (115200 bps).

parallel_rx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- parallel rx from uart_rx to FIFO_mf.

usedw_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- just a counter of FIFO.

);

END UART;

I used the Quartus II to associate those pins above from UART to the FPGA:

rst is a switch on the board.

serial_rx is the serial rx on the board DE2-70.

clock_50MHz is the 50MHz clock from the board..

rd is a button fr mthe board.

full is a red led from the board.

empty another red led.

mod_27_cnt not associated, it is just for simulation visualization.

parallel_rx is associated to 8 green LEDs .

usedw_out not associated, it is just for simulation visualization.

After load the code to the board, I opened the terminal (I use one from arduino app) and reset the switch (rst) on the board.

After, for testing, I write 1 on the terminal, then 2, then 3.

Then, I pressed the button (rd) and nothing happens.

The green leds would expected to be flashing the 1 binary at first press. Then the 2 binary after second pressing. The same with 3 binary.

It happens in the simulation with ModelSim Altera.

As I am a newbie with FPGA, I would expect the simulations, as soon as they are synthesizable, happens in the board too.

I attached the schematic from qartus II to help to visualize it.

All the role are played (I think it is) by the mod_27_uart, that starts to count from 0 to 12 (ignore the 14 in the image, I correct it) to detect the start bit, and from 0 to 12 twice to detect each of the 8 data bits, and finally to 0 to 12 to detect the end bit. The mod_27_uart only starts to cout when the start bits on uart_rx is detected, so it is why the uart_rx controls the reset of the mod_27_uart.

Please could some experienced help me with this issue?

I appreciate your help.