UART and MODELSIM ALTERA (code attached)

Hi friends, I have just a theoretical doubt about rx uart and I would appreciate if any help.

The system clock, provided for the board is 50Mhz, and I was needing a 115200bps UART.

I made a mod entity that outputs 1 tick every 13 ticks from the system clock including a 16 oversampling, based on this claculations:

16 is my choice for the number of oversampling for RX bits.

115200bps is the uart baud rate.

50Mhz is the system clock.

50Mhz/(16*115200) = 27,126736111 what I assumed to be 27.

So, if 50Mhz system clock has 20 ps in each cicle, after 27*20ps = 540 ps the mod entity would be generate one tick.

As soon as the start bit is detected, I am interested in sampling the middle of this bit, so, at 13ª cicle or 540ps/2 = 270 ps after this start bit is being detected.

All this explanation is to justify why I made the mod count from 0 to 12 to outputs one tick, for detecting the middle of start bit and after I wait two ticks of 0 to 12, I take the sample for data bits and stop bits.

It gives me a conversion from 50Mhz to 1/540ps = 1.851 Hz, what I think it is close to the1.8432Hz needed to 115200bps.

I attached the begin and the end of simulation.

Are that correct?

Thank you very much.