Hi,
Be careful, this post is quite long! but I think it has a lot of information...
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It's not clear to me, if the reported observations are only misinterpretation of simulation results or also in part indicating bad HDL coding. Somes lines of code should clarify this
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To be honnest it's not clear to me too!
I have tried this :
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feed the counter to an external port to see the real counter value. If the counter is actually counting wrong, bad coding must be expected.
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But both counters have differents values, and are also wrong!
This is the code I am using, I am looking after bit_number and ext_count (which is the port you asked me to add).
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.AD9854_DDFS;
entity Serial_NInterface_Driver2 is generic(Nb_ddfs:AD9854_DDFS.DEVICE_ID:=1);
port (clkin: IN STD_LOGIC ; -- external clock
reg_addr: IN AD9854_DDFS.SERIAL_ADDRESS;
reg_data : IN AD9854_DDFS.SERIAL_DATA;
load: IN STD_LOGIC;-- WHEN HIGH, reg_to_program HAS A NEW VALUE
mask: IN STD_LOGIC_VECTOR (1 TO Nb_ddfs);
busy: OUT STD_LOGIC; -- WHEN HIGH THE ENTITY IS BUSY TO TRANSMIT AND CAN NOT MANAGE ANY OTHER load
io_reset:OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs):=(others=>'1'); -- VECTOR TO ALL io_reset OUTPUT
csbOUT: OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs); -- VECTOR TO ALL csbOUT OUTPUT
sdclk:OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs);-- VECTOR TO ALL sdclk OUTPUT
sdio:OUT STD_LOGIC; -- POSSIBLY SHARED OUTPUT TO DDFS
sdo: OUT STD_LOGIC;-- POSSIBLY SHARED OUTPUT TO DDFS to earn pins, sdo pins on ddfs could be stuck to ground on pcb
-- Added port : --------------------------------------------------------------------
ext_count: OUT POSITIVE RANGE 1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT);
------------------------------------------------------------------------------
end Serial_NInterface_Driver2;
-- Architecture Body
ARCHITECTURE Serial_NInterface_Driver2_Architecture OF Serial_NInterface_Driver2 IS
SIGNAL transmiting :STD_LOGIC;
SIGNAL enable :STD_LOGIC_VECTOR(1 TO Nb_ddfs);
SIGNAL local_mask : STD_LOGIC_VECTOR(1 TO Nb_ddfs);
BEGIN
csbOUT<=not local_mask;
sdo<='0';
sdclk<= CONV_STD_LOGIC_VECTOR(NOT clkin,Nb_ddfs) AND enable;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--PROCESS 1
PROCESS (clkin)
BEGIN
IF clkin='1' AND transmiting='1' THEN
enable<=local_mask;
ELSIF transmiting='0' THEN
enable<=(others=>'0');
END IF;
END PROCESS;
--PROCESS 2
PROCESS (clkin)
VARIABLE Idle:BOOLEAN :=TRUE;
VARIABLE bit_number: POSITIVE RANGE 1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT:=1;
VARIABLE frame :STD_LOGIC_VECTOR(1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT ):=(others=> '0');
BEGIN
IF clkin='1' THEN
-- driver is idle
IF Idle THEN
busy<='0';
transmiting<='0';
sdio<='0';
io_reset<=(others=>'1');
bit_number:=frame'left;
--prepare the frame and set the right mask if load is high
--then change state
IF load='1' THEN
frame:="0000" & reg_addr & reg_data;
local_mask<=mask;
Idle:=FALSE;
END IF;
--driver is transmiting
ELSE
io_reset<=not local_mask;
busy<='1';
transmiting<='1';
IF bit_number<=8*(1+AD9854_DDFS.size_of_register(frame(5 TO 8))) THEN
sdio<=frame(bit_number);
bit_number:=bit_number+1;
-- FINALIZE TRANSMISSION
ELSE
transmiting<='0';
Idle:=TRUE;
END IF;
END IF;
-- I have just added this line
ext_count<=bit_number;
END IF;
END PROCESS;
END Serial_NInterface_Driver2_Architecture;
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Hi Dennis,
lets start from the basics. What kind of design description do you use Verilog ,VHDL,
schematic ... ? Did you get warnings from Quartus ? Which device are you using .....
Kind regards
GPK
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I am using both vhdl and schematics , and quartus give me a lot of warning (123) mainly on others blocks a I did not design. Here are warnings I get for the previous posted entity
Warning (10492): VHDL Process Statement warning at Serial_Ninterface_Driver2.vhd(47): signal "transmiting" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at Serial_Ninterface_Driver2.vhd(48): signal "local_mask" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at Serial_Ninterface_Driver2.vhd(49): signal "transmiting" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at Serial_Ninterface_Driver2.vhd(45): inferring latch(es) for signal or variable "enable", which holds its previous value in one or more paths through the process
..
Warning: Latch Serial_NInterface_Driver2:inst11|enable has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal clk
..
Warning: No exact pin location assignment(s) for 6 pins of 91 total pins
Info: Pin extcount not assigned to an exact location on the device
Info: Pin extcount not assigned to an exact location on the device
Info: Pin extcount not assigned to an exact location on the device
Info: Pin extcount not assigned to an exact location on the device
Info: Pin extcount not assigned to an exact location on the device
Info: Pin extcount not assigned to an exact location on the device
..
Warning: Timing Analysis found one or more latches implemented as combinational loops
..
Warning: Node "Serial_NInterface_Driver2:inst11|enable" is a latch
Warning: Found combinational loop of 1 nodes
Warning: Node "Serial_NInterface_Driver2:inst11|enable"
I have also "sdo" and "csb" stuck to the ground and obviously ext_count with no pin assignement
but nothing about my counter or my boolean Idle!
I am working with an altera cyclone II EP2C0Q240C8N
I hope you had the breath to read my post until this line!
and I thank you for that!
Denis
Honored Contributor
