Honored Contributor
Honored ContributorHi FvM,
Thanks for reply. --- Quote Start --- As far as I see, you don't have any edge sensitive conditions in your processes, so they are pure combinational. --- Quote End --- I though that the sensitivity list was sufficient. --- Quote Start --- Please consult the counter and state machine examples in the Quartus VHDL templates, they always have an expression like if rising_edge(clk) then. --- Quote End --- I have tried to follow this example http://www.altera.com/support/examples/vhdl/v_counters.html (http://www.altera.com/support/examples/vhdl/v_counters.html[/html) which give now :LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.AD9854_DDFS;
entity Serial_NInterface_Driver2 is generic(Nb_ddfs:AD9854_DDFS.DEVICE_ID:=1);
port (clkin: IN STD_LOGIC ; -- external clock
reg_addr: IN AD9854_DDFS.SERIAL_ADDRESS;
reg_data : IN AD9854_DDFS.SERIAL_DATA;
load: IN STD_LOGIC;-- WHEN HIGH, reg_to_program HAS A NEW VALUE
mask: IN STD_LOGIC_VECTOR (1 TO Nb_ddfs);
busy: OUT STD_LOGIC; -- WHEN HIGH THE ENTITY IS BUSY TO TRANSMIT AND CAN NOT MANAGE ANY OTHER load
io_reset:OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs):=(others=>'1'); -- VECTOR TO ALL io_reset OUTPUT
csbOUT: OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs); -- VECTOR TO ALL csbOUT OUTPUT
sdclk:OUT STD_LOGIC_VECTOR (1 TO Nb_ddfs);-- VECTOR TO ALL sdclk OUTPUT
sdio:OUT STD_LOGIC; -- POSSIBLY SHARED OUTPUT TO DDFS
sdo: OUT STD_LOGIC--;-- POSSIBLY SHARED OUTPUT TO DDFS to earn pins, sdo pins on ddfs could be stuck to ground on pcb
-- Added port : --------------------------------------------------------------------
--ext_count: OUT POSITIVE RANGE 1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT
);
------------------------------------------------------------------------------
end Serial_NInterface_Driver2;
-- Architecture Body
ARCHITECTURE Serial_NInterface_Driver2_Architecture OF Serial_NInterface_Driver2 IS
SIGNAL transmiting :STD_LOGIC;
SIGNAL enable :STD_LOGIC_VECTOR(1 TO Nb_ddfs);
SIGNAL local_mask : STD_LOGIC_VECTOR(1 TO Nb_ddfs);
BEGIN
csbOUT<=not local_mask;
sdo<='0';
sdclk<= CONV_STD_LOGIC_VECTOR(NOT clkin,Nb_ddfs) AND enable;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--PROCESS 1
SERIAL_CLK_PROCESS:PROCESS (clkin)
BEGIN
IF rising_edge(clkin) THEN
IF transmiting='1' THEN
enable<=local_mask;
ELSIF transmiting='0' THEN
enable<=(others=>'0');
END IF;
END IF;
END PROCESS;
--PROCESS 2
SERIAL_TRANSMISSION_PROCESS: PROCESS (clkin)
VARIABLE Idle:BOOLEAN :=TRUE;
VARIABLE bit_number: POSITIVE RANGE 1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT:=1;
VARIABLE frame :STD_LOGIC_VECTOR(1 TO AD9854_DDFS.SERIAL_FRAME_SIZE'RIGHT ):=(others=> '0');
BEGIN
IF rising_edge(clkin) THEN
-- driver is idle
IF Idle THEN
busy<='0';
transmiting<='0';
sdio<='0';
io_reset<=(others=>'1');
bit_number:=frame'left;
--prepare the frame and set the right mask if load is high
--then change state
IF load='1' THEN
frame:="0000" & reg_addr & reg_data;
local_mask<=mask;
Idle:=FALSE;
END IF;
--driver is transmiting
ELSE
io_reset<=not local_mask;
busy<='1';
transmiting<='1';
IF bit_number<=8*(1+AD9854_DDFS.size_of_register(frame(5 TO 8))) THEN
sdio<=frame(bit_number);
bit_number:=bit_number+1;
-- FINALIZE TRANSMISSION
ELSE
transmiting<='0';
Idle:=TRUE;
END IF;
END IF;
END IF;
-- I have just added this line
--ext_count<=bit_number;
END PROCESS;
END Serial_NInterface_Driver2_Architecture;Warning: Ignored node in vector source file. Can't find corresponding node name
