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Altera_Forum
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16 years ago

tricky problems

Hi everybody, I am currently using Quartus II 9.0sp2 Web Edition in order to program an FPGA for a research project ( I am a trainee, my knowledges of quartus are quite fresh). I ha...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It's not clear to me, if the reported observations are only misinterpretation of simulation results or also in part indicating bad HDL coding. Somes lines of code should clarify this.

Regarding the counter issue:

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- some values are in the wrong order (3,2,5,4,7,6,9,8 instead of 1,2,3,4,5,6,7,8,9)

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It may be the case, that you are reading an internal counter value, that is using a different internal coding due to optimizations. You should feed the counter to an external port to see the real counter value. If the counter is actually counting wrong, bad coding must be expected.